Signal Integrity Issues and Printed Circuit Board Design by Douglas Brooks

Signal Integrity Issues and Printed Circuit Board Design Douglas Brooks ebook
Publisher: Prentice Hall International
Format: djvu
Page: 409
ISBN: 013141884X, 9780131418844

When designing the PCB, contradictory goals of power delivery with high integrity and bi-directional signal integrity need to be balanced. A successful high-speed PCB must effectively integrate high speed ASIC's and other components to optimize signal integrity. However, this feature is not available in the Allegro PCB Editor tool. PCB design is mostly about signal integrity, controlled impedance lines, EM coupling, and supply decoupling. Our APD AE expert, and in the SPB16.3 APD tool, there is an Edit> Cline Change Width command. Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. With 35 designers, we are one of the largest layout service providers in North America specializing in high-performance PCB design. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance. At these high transmission rates, signal integrity issues become increasingly restrictive on PCB trace and cable lengths, and on design implementation and features. In IC package design, it is becoming increasingly necessary to change a cline's width in a given region, whether for signal integrity reasons or to allow all necessary traces to pass through a particularly dense region. As system operating frequencies are increasing, PCB layout is becoming increasingly complex. I don't know of a good reference that addresses all the issues. DesignCon 2012 promises to address issues around PCB design tools, RF and signal integrity, FPGA design, IC and semiconductor components, verification tools, and high-speed serial design. Grzenia on March 25, 2009Comments(2)Filed under: PCB design, SPB 16.2, Cline change, APD.